The invention pertains to methods of forming electrical connection to semiconductor electrical nodes, and to structures comprising electrical connections to semiconductor electrical nodes.
Semiconductor device fabrication frequently includes formation of diffusion regions in silicon-comprising substrates, and subsequent formation of electrical contacts to the diffusion regions. The diffusion regions can, for example, be source/drain regions associated with transistor gates, and the silicon-comprising substrates can, for example, be either polycrystalline silicon, amorphous silicon, or monocrystalline silicon.
Several methods have been developed for forming electrical contacts to diffusion regions, but frequently problems are associated with the methods. For instance, one method of forming an electrical contact to a diffusion region is simply to physically contact the diffusion region with an electrical interconnect comprising conductively-doped silicon. Such methodology can be effective in applications in which the diffusion region and the conductively-doped silicon are both doped to a same conductivity type (for example, in which the diffusion region and the conductively-doped silicon of the interconnect are both doped to be n-type). However, if the conductively-doped silicon interconnect has a different conductivity type than the diffusion region, the interconnect cannot simply be physically contacted with the diffusion region or a diode will develop at an interface of the interconnect and the diffusion region.
It is common for both n-type and p-type diffusion regions to be formed across a silicon-containing substrate, and it is frequently desired to simultaneously form conductive contacts with both the p-type diffusion regions and the n-type diffusion regions. Further, since it is usually easier to form n-type doped silicon as a conductive interconnect than p-type doped silicon, it can be desired to form n-type doped silicon as a conductive interconnect material across an entirety of a substrate. However, for the reasons discussed above, an n-type doped silicon interconnect can generally not be utilized to directly contact a p-type doped diffusion region, and accordingly it is generally not practical to form n-type doped silicon interconnects extending to both p-type doped diffusion regions and n-type doped diffusion regions.
Several methods have been developed to overcome the above-described problem. One method is to mask all of the n-type doped diffusion regions, and to then form p-type doped polysilicon interconnects extending to the p-type doped diffusion regions. Subsequently, the mask is formed over the p-type doped polysilicon interconnects and p-type doped diffusion regions, and n-type doped silicon interconnects are formed to the n-type doped regions. Another method which has been developed is to form a conductive layer over the p-type diffusion regions and n-type diffusion regions, and to subsequently form the n-type doped silicon over the conductive layer. The conductive layer typically comprises metal silicide (either alone or in combination with layers of metal nitride and/or other metal-comprising layers), and prevents the direct physical connection of n-type polysilicon with p-type polysilicon. The conductive layer accordingly eliminates interfaces between n-type doped silicon and p-type doped silicon, and the problems associated therewith.
The utilization of conductive layers as interfaces between diffusion regions and interconnecting conductively-doped silicon is becoming particularly common in fabrication processes in which p-type doped diffusion regions and n-type doped diffusion regions occur in close proximity to one another, such as, for example, in applications in which memory circuitry has logic circuitry embedded therein (such as, for example, so-called embedded dynamic random access memory, also known as EDRAM.)
Metal silicide layers are typically formed over diffusion regions by depositing metal on the diffusion regions, and then subsequently reacting the metal with silicon of the diffusion regions to form the metal silicide. A difficulty with such processing is that a significant amount of silicon can be utilized in forming the metal silicide, which can reduce an effective size of a diffusion region. Such problems can be severe in applications in which diffusion regions are initially shallow.
Another problem that can occur in forming the metal silicide is specific for particular types of metal silicide. For instance, a commonly utilized metal silicide is titanium silicide. However, titanium silicide can agglomerate at processing conditions generally utilized for formation of semiconductor devices (such as, for example, processing conditions of 850xc2x0 C. to 1,000xc2x0 C.), and can thus become a less effective conductive material than is desired for particular applications.
It would be desirable to develop new structures for electrically contacting diffusion regions, and to develop methodology for forming such structures.
In one aspect, the invention encompasses a method of forming a semiconductor construction. A metal-rich metal silicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen.
In another aspect, the invention encompasses a method of forming a semiconductor construction in which a composition of TaSix is formed on a silicon-comprising substrate, with the x being less than 2. A tungsten nitride layer is formed over the composition TaSix, and a tungsten layer is formed over the tungsten nitride layer. Subsequently, silicon is incorporated from the silicon-comprising substrate into the TaSix to convert at least some of the TaSix into TaSi2.
In other aspects, the invention encompasses semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.